Communication devices and other electronic equipment use a variety of active devices including digital and analog ICs. Increased data clock rates and densely packed active components create an ideal environment for electromagnetic interference (EMI) as well as create ground bounce and Vcc droop. This interference contributes to jitter and timing problems within the integrated circuits and its impact on performance is difficult to model using simulations therefore it needs to be verified early in the design cycle. Noisecom JV9000 generates random noise (AWGN) and deterministic (CW) signals and injects them to the power supply (Vcc) in a controlled fashion to allow the user to test their device, circuit or system performance against noise on Vcc.

Modern integrated circuits contain billions of transistors that require complex power distribution systems. This power distribution complexity combined with inexpensive switch-mode power supplies creates several sources of noise found on the power and ground planes of a PC circuit board. This interference is difficult to model using software and contributes to jitter timing problems within the IC. The Noisecom JV9000A is designed to generate random and deterministic noise on the power and ground planes to emulate this behavior. The webinar illustrates how the JV9000A can be used to generate these effects in real systems.

A noise source that produces white noise is essentially an inexpensive broadband signal generator with an extremely flat (constant) power density output versus frequency. Noise sources are almost insensitive to temperature and supply voltage variations. Noise sources are therefore used for Built-in Testing (BIT), Fault Isolation Testing (FIT), and calibration in communication and radar warning systems to ensure the reliability and performance of the link. The webinar will be about the discussion of noise relevant parameters and applications.

Serial data systems play an increasingly important role whenever volumes of data are processed or transported. Jitter is a key concern for engineers developing high speed components such as transmitters, receivers and data channels. Serial high speed communication systems need to operate within very tight margins; with data provided extremely fast and with an exceptionally low probability of errors.

Data transmission is often conducted under very difficult circumstances; weak signals that transport high data rates within an unfavorable noise environment have to be recognized by receivers. Furthermore, data streams have to be transmitted reliably and with low BER. Designers, developers and system engineers have to take less-than-ideal circumstances in consideration when they design their circuits or monitor their system.